1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a method of forming a gate dielectric with an increased thickness in regions of the integrated circuit proximal to boundaries of the isolation structures.
2. Description of the Relevant Art
The fabrication of MOS (metal-oxide-semiconductor) transistors within a semiconductor substrate is well known. Typically, the substrate is divided into a plurality of active and isolation regions through an isolation process such as field oxidation or shallow trench isolation. A thin oxide is then grown on an upper surface of the semiconductor substrate in the active regions. This thin oxide serves as the gate oxide for subsequently formed transistors. Next, a plurality of polysilicon gate structures are formed wherein each polysilicon gate traverses an active region effectively dividing the active region into two regions referred to as the source region and the drain region. After formation of the polysilicon gates, an implant is performed to introduce an impurity distribution into the source/drain regions.
As transistor channels shrink below 0.5 microns, the limitations of conventional transistor processing become more apparent. To combat short channel effects in deep sub-micron transistors, the depth of the source/drain junctions and the thickness of the gate oxides must be reduced. Devices become more susceptible, however, to breakdown due to electrical stress across the oxide. In a conventional sub-half-micron transistors, for example, gate dielectric thickness in the range of approximately 50 angstroms are not uncommon. If a 3.3 volt potential is applied across this film, a common occurrence in MOS transistors, the resulting electrical field has a nominal value in the range of approximately 3.3 MV/cm. In regions of the underlying gate dielectric proximate to geometric discontinuities, a localized electric field can greatly exceed the nominal value and can cause dielectric breakdown. Accordingly, it has been theorized that the gate dielectric is more likely to breakdown in regions of the device adjacent or proximal to isolation structures and, more particularly, shallow trench isolation structures, where discontinuities in the underlying substrate are common and can result in electrical fields exceeding 6 MV/cm, which is considered to be an upper limit on the electrical field sustainable by a thermally formed SiO.sub.2 film. See, e.g., 1 S. Wolf & R. Tauber, Silicon Processing for the VLSI Era 183 (Lattice Press 1986) [hereinafter "Wolf Vol. 1"].
Despite the problem of dielectric, thin gate dielectrics are desirable in the active regions of a device because the transistor drive current is inversely proportional to the gate oxide thickness over a wide range of operating conditions. Because higher drive currents result in faster devices, a great deal of effort has been directed towards reducing the gate oxide thickness (as well as other transistor geometries including channel length and junction depth) without significantly reducing the reliability of the integrated circuit.
Therefore, it would be highly desirable to fabricate a gate dielectric that simultaneously possessed the requisite thinness in critical active regions of the device and an improved resistance to dielectric breakdown in regions of the device proximal to discontinuities in the dielectric.